Research Catalog
FireWire system architecture : IEEE 1394a
- Title
- FireWire system architecture : IEEE 1394a / MindShare, Inc. ; Don Anderson.
- Author
- Anderson, Don, 1953-
- Publication
- Reading, Mass. : Addison-Wesley, [1999], ©1999.
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1 Item
| Status | Format | Access | Call Number | Item Location |
|---|---|---|---|---|
| Text | Request in advance | TK7895.B87 A52 1999 | Off-site |
Details
- Additional Authors
- MindShare, Inc.
- Description
- xxxiii, 509 pages : illustrations; 24 cm.
- Summary
- The FireWire (IEEE 1394a) standard for high-speed serial bus communications has come to the fore as an important technology supporting today's emerging data-intensive applications.
- FireWire System Architecture provides an in-depth description of the IEEE 1394a cable environment, based on the 2.0 version of the 1394a standard. Comprehensive, concise, and well-organized, this book details the specification itself and presents the architecture, features, and operations of systems developed with the FireWire bus.
- Completely up-to-date, this new edition covers all of the changes incorporated into the 2.0 standard, such as arbitration enhancements, improvements in bus reset timing, new PHY register definition, and port interface enhancements to support suspend/resume and port disable. In addition, it provides in-depth information on suspend/resume operation, power distribution, and power management.
- Series Statement
- PC system architecture series
- Uniform Title
- PC system architecture series.
- Subject
- Note
- Includes index.
- Contents
- Pt. 1. Introduction to FireWire (IEEE 1394a). Ch. 1. Why FireWire? Ch. 2. Overview of the IEEE 1394 Architecture -- Pt. 2. Serial Bus Communications. Ch. 3. Communications Model. Ch. 4. Communications Services. Ch. 5. Cables & Connectors. Ch. 6. The Electrical Interface. Ch. 7. Arbitration. Ch. 8. Asynchronous Packets. Ch. 9. Isochronous Packet. Ch. 10. PHY Packet Format. Ch. 11. Link to PHY Interface. Ch. 12. Transaction Retry -- Pt. 3. Serial Bus Configuration. Ch. 13. Configuration Process. Ch. 14. Bus Reset (Initialization). Ch. 15. Tree Identification. Ch. 16. Self Identification -- Pt. 4. Serial Bus Management. Ch. 17. Cycle Master. Ch. 18. Isochronous Resource Manager. Ch. 19. Bus Manager. Ch. 20. Bus Management Services -- Pt. 5. Registers & ROM. Ch. 21. CSR Architecture. Ch. 22. PHY Registers. Ch. 23. Configuration ROM -- Pt. 6. Power Management. Ch. 24. Introduction to Power Management. Ch. 25. Cable Power Distribution.
- Ch. 26. Suspend & Resume. Ch. 27. Power State Management.
- ISBN
- 0201485354
- LCCN
- 98043465
- OCLC
- ocm40200319
- Owning Institutions
- Columbia University Libraries